Huawei LogicFolding%3A stacks two active silicon layers face-to-face via 1.5um hybrid bonding instead of shrinking transistors. SMIC 7nm made with 193nm immersion DUV plus self-aligned quadruple patterning. Density jumped 155 to 138MTr%2Fmm² (%2B55%)%2C like three node generations ahead but silicon unchanged. Roadmap to 3-4%2B layers over next decade%3B heat trapping and compounding yield are main limits. Chinese EUV prototype built in Shenzhen early 2025 by ex-ASML engineers%3B generates 13.5nm light but no working chips yet. Gov target 2028%2C realistic 2030.